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| a FEATURES Low Power: 940 mW 53 dB SNR @ 10 MHz AIN On-Chip T/H, Reference CMOS-Compatible 2 V p-p Analog Input Fully Characterized Dynamic Performance APPLICATIONS Ultrasound Medical Imaging Digital Oscilloscopes Professional Video Digital Communications Advanced Television (MUSE Decoders) Instrumentation ENCODE AIN GND T/H 10-Bit 40 MSPS A/D Converter AD9040A FUNCTIONAL BLOCK DIAGRAM AMP ARRAY T/H VOUT BANDGAP REFERENCE 5-BIT ADC 6-BIT ADC VREF REF AMP ERROR CORRECTION BPREF DECODE LOGIC DECODE LOGIC AD9040A 10 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9040A is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with on-board track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only an encode signal to achieve 40 MSPS sample rates with 10-bit resolution. Digital inputs and outputs are CMOS compatible; the analog input requires a signal of 2 V p-p amplitude. The two-step architecture used in the AD9040A is optimized to provide the best dynamic performance available while maintaining low power requirements of only 940 mW typically; maximum dissipation is 1.1 watt at 40 MSPS. The signal-to-noise ratio (SNR), including harmonics, is 53 dB, or 8.5 ENOB, when sampling an analog input of 10.3 MHz at 40 MSPS. Competitive devices perform at less than 7.5 ENOB and require external references and larger input signals. The AD9040A A/D converter is available as either a 28-lead plastic DIP or a 28-lead SOIC. The two models operate over a commercial temperature range of 0C to +70C. Contact the factory regarding availability of ceramic military temperature range devices. 1. CMOS compatible logic for direct interface to ASICs. 2. On-board T/H provides excellent high frequency performance on analog inputs, critical for communications and medical imaging applications. 3. High input impedance and 2 volt p-p input range reduce need for external amplifiers. 4. Easy to use; no cumbersome external voltage references required, allowing denser packing of ADCs for multichannel applications. 5. Available in 28-lead plastic DIP and SOIC packages. 6. Evaluation board includes AD9040AJR, reconstruction DAC, and latches. Space is available near the analog input and digital outputs of the converter for additional circuits. Order as part number AD9040A/PCB (schematic shown in data sheet). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD9040A-SPECIFICATIONS= V = +5 V; -V = -5 V; internal reference: ENCODE = 40.5 MSPS unless (+V ELECTRICAL CHARACTERISTICS Parameter (Conditions) RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error Gain Tempco1 ANALOG INPUT Input Voltage Range Input Offset Voltage Input Bias Current Input Resistance Input Capacitance Analog Bandwidth BANDGAP REFERENCE Output Voltage Temperature Coefficient1 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio3 fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio3 (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio3, 4 fIN = = 2.3 MHz fIN = = 10.3 MHz Signal-to-Noise Ratio3, 4 (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz 2nd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz 3rd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz Two-Tone Intermodulation Distortion Rejections Differential Phase Differential Gain +25C Full +25C Full Full +25C Full Full +25C +25C Full +25C Full +25C +25C +25C Full Full +25C +25C +25C +25C +25C Full +25C +25C +25C +25C I VI I VI VI I VI V V I VI I VI I V V VI V I IV V V I IV V V I I 51 50 S D S otherwise noted) Test Level Min AD9040AJN/JR Typ 10 1.0 1.0 Guaranteed 0.5 70 2 2 7 200 350 5 48 2.6 2.0 2.5 2.0 2.5 1.5 2 Max Units Bits LSB LSB LSB LSB % FS % FS ppm/C V p-p mV mV A A k pF MHz V ppm/C MSPS MSPS ns ps, rms ns ns ns ns dB dB Temp 25 30 15 25 2.4 40 40 2 1.9 7 10 10 7.5 6 12 14 25 40 54 53 +25C +25C +25C +25C I I I I 52 51 52 51 55 54 56 55 dB dB dB dB +25C +25C +25C +25C +25C +25C +25C +25C +25C I I I I I I V III III -2- 53 53 56 56 58 58 57 56 67 65 73 70 62 0.15 0.25 0.5 1.0 dB dB dBc dBc dBc dBc dBc Degrees % REV. B AD9040A Parameter (Conditions) ENCODE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth (High) (tEH)6 Encode Pulsewidth (Low) (tEL)6 DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY VD Supply Current +VS Supply Current -VS Supply Current Power Dissipation Power Supply Rejection Ratio (PSRR)7 Temp Full Full Full Full +25C +25C +25C Full Full Test Level VI VI VI VI V IV IV VI VI Min 4.0 1.0 1 1 14 10 10 4.95 0.05 Offset Binary Full Full Full Full +25C VI VI VI VI I ABSOLUTE MAXIMUM RATINGS 1 AD9040AJN/JR Typ Max Units V V A A pF ns ns V V 100 100 13 89 87 0.94 20 110 105 1.2 15 mA mA mA W mV/V NOTES 1 "Gain Tempco" is for converter using internal reference; "Temperature Coefficient" is for bandgap reference only. 2 Output propagation delay (t PD) is measured from the 50% point of the falling edge of the encode command to the min/max voltage levels of the digital outputs with 10 pF maximum loads. 3 RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency. 4 ENCODE = 32 MSPS. 5 3rd order intermodulation measured with analog input frequencies of 2.3 MHz and 2.4 MHz at 7 dB below full scale. 6 For rated performance at 40 MSPS, duty cycle of encode command should be 50% 10%. 7 Measured as the ratio of the change in offset voltage for a 5% change in +V S or -VS. Specifications subject to change without notice. VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS to +VS DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +VS VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature AD9040AJN/JR . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature2 (JN/JR Suffixes) . . . +150C Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300C NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (parts soldered to board): N Package (Plastic DIP): JA = 42C/W; JC = 10C/W. R Package (SOIC): JA = 47C/W; JC = 10C/W. EXPLANATION OF TEST LEVELS Test Level I - 100% Production Tested. II - 100% production tested at +25C, and sample tested at specified temperatures. AC testing done on sample basis. III - Sample Tested Only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. ORDERING GUIDE Model AD9040AJN AD9040AJR AD9040A/PWB AD9040A/PCB Temperature Range Package Description Package Option N-28 R-28 0C to +70C 28-Lead Plastic DIP 0C to +70C 28-Lead SOIC Package Printed Circuit Board (Only) of Evaluation Circuit Complete Evaluation Board, Assembled and Tested, Including AD9040AJR -3- REV. B AD9040A N N+1 AIN MIN TYP 1.9 10 10 7.5 10ns 100 100 12 MAX tA ENCODE #2 #3 tA tEH tEL tPD APERTURE DELAY PULSEWIDTH HIGH PULSEWIDTH LOW OUTPUT PROP DELAY tEH tEL tPD DIGITAL OUTPUTS N-3 N-2 N-1 Figure 1. Timing Diagram PIN FUNCTION DESCRIPTIONS -VS 1 28 27 26 25 24 D0 (LSB) D1 D2 D3 D4 VD Pin No. 1, 12, 21 2, 4, 11, 14, 22 3, 10 5 6 Name -VS GND +VS VOUT Function GND 2 +VS 3 GND 4 VOUT 5 VREF 6 BPREF 7 ENCODE 9 +VS 10 GND 11 -VS 12 AIN 13 GND 14 7 8 9 13 15 16 17-20 23 24-27 28 D1 D0 (LSB) DIE LAYOUT AND MECHANICAL INFORMATION Die Dimensions . . . . . . . . . . . . . . . . . 204 x 185 x 21 ( 1) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-VS Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,070 Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach (JN/JR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy Bond Wire (JN/JR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold GND -VS +VS 5 V Power Supply Ground Analog +5 V Power Supply Internal Bandgap Voltage Reference (Nominally +2.5 V) VREF Noninverting Input to Reference Amplifier. Voltage reference for ADC is connected here. BPREF External Connection for (0.1 F) Reference Bypass Capacitor NC No Connection Internally ENCODE Encode Clock Input to ADC. Internal T/H placed in hold mode (ADC is encoding) on rising edge. AIN Noninverting Input to T/H Amplifier OR Out-of-Range Condition Output. Active high when analog input exceeds input range of ADC by 1 LSB ( GND TOP VIEW NC 8 (Not to Scale) 21 -VS 22 20 19 18 17 16 15 AD9040A 23 D5 D6 D7 D8 D9 (MSB) OR NC = NO CONNECT PDIP and SOIC Pinouts D9 (MSB) GND AIN D7 +VS D6 D5 -VS DGND VD D4 D3 D2 BPREF VREF ENCODE D8 OR -VS GND NC VOUT GND -4- REV. B AD9040A DEFINITIONS OF SPECIFICATIONS Maximum Conversion Rate Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. Aperture Delay The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the falling edge of the ENCODE command and the 1 V/4 V points of output data. Overvoltage Recovery Time The delay between the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The amount of time required for the converter to recover to 10-bit accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. Power Supply Rejection Ratio (PSRR) The sample-to-sample variation in aperture delay. Differential Gain The percentage of amplitude change of a small high frequency sine wave (3.58 MHz) superimposed on a low frequency signal (15.734 kHz). Differential Nonlinearity The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise Ratio (SNR) The deviation of any code from an ideal 1 LSB step. Differential Phase The ratio of the rms signal amplitude to the rms value of "noise," which is defined as the sum of all other spectral components, including harmonics but excluding dc, with an analog input signal 1 dB below full scale. Signal-to-Noise Ratio (Without Harmonics) The phase change of a small high frequency sine wave (3.58 MHz) superimposed on a low frequency signal (15.734 kHz). Harmonic Distortion The rms value of the fundamental divided by the rms value of the harmonic. Integral Nonlinearity The ratio of the rms signal amplitude to the rms value of "noise," which is defined as the sum of all other spectral components, excluding the first eight harmonics and dc, with an analog input signal 1 dB below full scale. Transient Response The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The time required for the converter to achieve 10-bit accuracy when a step function is applied to the analog input. Two-Tone Intermodulation Distortion (IMD) Rejection The encode rate at which the SNR of the lowest analog signal frequency tested drops by no more than 3 dB below the guaranteed limit. VCC VCC 1k 1k 1k 1k The ratio of the power of either of two input signals to the power of the strongest third-order IMD signal. VCC VCC VREF AIN 2k 6.8k 1mA VSS ANALOG INPUT REFERENCE CIRCUIT VSS BANDGAP OUTPUT CMOS OUTPUT 1mA GND BPREF GND GND RL 2.5k RL VOUT D0-9 Figure 2. Equivalent Circuits REV. B -5- AD9040A THEORY OF OPERATION Refer to the block diagram. The AD9040A employs subranging architecture and digital error correction. This combination of design techniques insures true 10-bit accuracy at the digital outputs of the converter. At the input, the analog signal is applied to a track-and-hold (T/H) that holds the analog value which is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse, which should have a 50% ( 10%) duty cycle. Minimum encode rate of the AD9040A is 10 MSPS because of the use of three internal T/H devices. The held analog value of the first track-and-hold is applied to a 5-bit flash converter and a pair of internal T/Hs (shown in the block diagram as a single unit). The T/Hs pipeline the analog signal to the amplifier array through a residue ladder and switching circuit while the 5-bit flash converter resolves the most significant bits (MSBs) of the held analog voltage. When the 5-bit flash converter has completed its cycle, its output activates 1-of-32 ladder switches; these, in turn, cause the correct residue signal to be applied to the error amplifier array. The output of the error amplifier is applied to a 6-bit flash converter whose output supplies the five least significant bits (LSBs) of the digital output along with one bit of error correction for the 5-bit main range converter. Decode logic aligns the data from the two converters and presents the result as a 10-bit parallel digital word. The output stage of the AD9040A is CMOS. Output data are strobed on the trailing edge of the ENCODE command. Full-scale range of the AD9040A is determined by the reference voltage applied to the VRFF (Pin 6) input. This voltage sets the internal flash and residue ladder voltage drops; these establish the value of the LSB. Because of headroom restraints, the fullscale range cannot be increased by applying a higher-than specified reference voltage. Conversely, a lower reference voltage will reduce the full-scale range of the converter, but will also decrease its performance. An internal bandgap reference voltage of +2.5 V is provided to assure optimum performance over the operating temperature range. USING THE AD9040A (tPD) after the falling edge of the encode command (refer to AD9040A Timing Diagram). The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9040A; these transients can detract from the converter's dynamic performance. Voltage Reference A stable voltage reference is required to establish the 2-V p-p range of the AD9040A. There are two options for creating this reference. The easiest and least expensive way to implement it is to use the (+2.5 V) bandgap voltage reference which is internal to the ADC. Figure 3 illustrates the connections for using the internal reference. The internal reference has 500 A of extra drive current which can be used for other circuits. AD9040A VOUT +2.5V BANDGAP REFERENCE VREF REF AMP REFERENCE 0.1 F BPREF -VS Figure 3. Using Internal Reference Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain (input range) of the AD9040A which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used, as shown in Figure 4. The VREF input requires 5 A of drive current. AD9040A VOUT BANDGAP REFERENCE REF AMP REFERENCE VREF REFERENCE 0.1 F Timing The duty cycle of the encode clock for the AD9040A is critical for obtaining rated performance of the ADC. Internal pulse widths within the track-and-hold are established by the encode command pulse width; to ensure rated performance, the duty cycle should be held at 50%. Duty cycle variations of less than 10% will cause no degradation in performance. Operation at encode rates less than 10 MSPS is not recommended. The internal track-and-hold saturates, causing erroneous conversions. This T/H saturation precludes clocking the AD9040A in burst mode. The 50% duty cycle must be maintained even for sample rates down to 10 MSPS. The AD9040A provides latched data outputs, with 2 1/2 pipeline delays. Data outputs are available one propagation delay 0.1 F BP REF -VS Figure 4. Using External Reference -6- REV. B AD9040A In applications using multiple AD9040As, slaving the reference inputs to a single reference output will improve gain tracking among the ADCs, as shown in Figure 5. AD9040A VOUT VREF 0.1 F 0.1 F -VS GAIN CONTROL VOLTAGE +625mV -625mV Time-Gain Control ADC Ultrasound and sonar systems require an increase in gain versus time. This allows the system to correct for attenuation of return pulses. Figure 6 shows the AD600/AD602 amplifier and the AD9040A ADC configured as a time-gain control analog-todigital converter. The control voltage ramps from -625 mV to +625 mV, permitting 40 dB of gain-control range. The voltage used for gain control can be either a linear ramp, or the output of a voltage-output DAC such as the AD7242. AD9040A VREF 0.1 F AIN AD600/602 AD9040A 0.1 F -VS AD9040A VREF 0.1 F 0.1 F -VS Figure 6. Ultrasound/Sonar Time-Gain Control ADC Using X-AMPsTM Transient Response Figure 7 illustrates the method for evaluating ADC transient performance. Two synthesizers are locked in synchronization, but tuned to frequencies which are slightly offset from a 2-to-1 submultiple. One synthesizer clocks a flat pulse network at a frequency of 19.9609375 MHz to provide the analog input signal; the other synthesizer output is shaped to provide a CMOS 40 MHz sampling clock. At the output of the AD9040A, output data reflects an interleaved alias of the input pulse. The repetitive sampling allows the measurement of ADC transient response as shown in performance graphs elsewhere in this data sheet. MARCONI 2030 SYNTHESIZER REF 19.9609375 MHz ENCODE ANALOG IN Figure 5. Slaving Multiple AD9040As to a Single Internal Reference In the specifications table, the Gain Tempco parameter under DC ACCURACY applies to the ADC when the internal reference is being used. If an external reference is used, its temperature coefficient must be taken into account to determine overall temperature performance. The input range can be varied by adjusting the reference voltage applied to the AD9040A. By decreasing the reference voltage, the gain can be reduced approximately 10% with no degradation in performance. Increasing the reference voltage increases the gain; but for proper operation, the reference voltage should not exceed +2.6 V. FLAT PULSE NETWORK AD9040A OUTPUT MARCONI 2030 SYNTHESIZER REF 40 MHz SINE TO CMOS Figure 7. Transient Response Test X-AMP is a trademark of Analog Devices, Inc. REV. B -7- AD9040A Layout Information Preserving the accuracy and dynamic performance of the AD9040A requires that designers pay special attention to the layout of the printed circuit board. Analog paths should be kept as short as possible and be properly terminated to avoid reflections. The analog input and reference voltage connections should be kept away from digital signal paths; this reduces the amount of digital switching noise which is capacitively coupled into the analog section. Digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. The AD9040A digital outputs should be buffered or latched close to the device (<2 cm). This prevents load transients which may feedback into the device. In high speed circuits, layout of the ground is critical. A single, low impedance ground plane on the component side of the board is recommended. Power supplies should be capacitively coupled to the ground plane with high quality chip capacitors to reduce noise in the circuit. Multilayer boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance ground planes. In systems with dedicated analog and digital grounds, all grounds of the AD9040A should be connected to the analog ground plane. The power supplies of the AD9040A should be isolated from the supplies used for external devices; this reduces the amount of noise coupled into the ADC. The digital +5 volt connection of the device (VD, Pin 23) powers the digital outputs and should be connected to the same supply as +VS (Pins 3 and 10). Connecting VD to a system digital supply may couple noise into the device. Sockets limit dynamic performance and are not recommended for use with the AD9040A. EVALUATION BOARD performance without (or prior to) developing a user-specific printed circuit board. The two-sided board includes a reconstruction DAC and digital output interface, and uses the layout and applications suggestions outlined above. It is available from Analog Devices at nominal cost. Generous space is provided near the analog input and digital outputs to support additional signal processing components the user may wish to add. This prototyping area includes through holes with 100-mil centers to support a variety of component additions. Input/Output/Supply Information Power supply, analog input, clock connections, and reconstructed output (RC OUTPUT) are identified by labels on the evaluation board. Operation of the evaluation board should conform to the following characteristics: Table I. Evaluation Board Characteristics Parameter Supply Current +5 V -5.2 V AIN Impedance Voltage Range CLOCK Impedance Frequency RC OUTPUT Impedance Voltage Range Analog Input Typical 250 300 51 1.0 51 40 51 0 V to -1 V Units mA mA V MSPS V The evaluation board for the AD9040A (AD9040A/PCB) provides an easy and flexible method for evaluating the ADC's Analog input signals can be fed directly into the Device Under Test input (AIN). The AIN input is terminated at the device with a 51 resistor. -8- REV. B AD9040A Figure 8. PCB Top View DAC Reconstruction Figure 9. PCB Bottom View Table II. Digital Coding The AD9040A evaluation board provides an onboard AD9721 reconstruction DAC for observing the digitized analog input signal. The AD9721 is terminated into 51 ohms to provide a 1 V p-p signal at the output (RC OUTPUT). Output Data Analog Input Voltage Level Out-ofRange Digital Output MSB . . . LSB 1111111111 1111111111 1111111110 1100000000 1011111111 10000000000 01111111111 0100000000 0011111111 0000000001 0000000000 0000000000 The output data bits are latched with a CMOS 74AC574 which drives a 40-pin connector (AMP p/n 102153-9). The data and clock signals are available on the connector per the pin assignments shown on the schematic of the evaluation board. Output data are available on the falling edge of the clock. +1.002 V Positive Full Scale + 1 LSB 1 Positive Full Scale 0 +1 V Full Scale - 1 LSB 0 +1/2 V 0V -1/2 V Positive 1/2 Scale 1/2 Scale - 1 LSB Bipolar Zero 1/2 Scale + 1 LSB Negative 1/2 Scale Full Scale + 1 LSB Negative Full Scale 0 0 0 0 0 0 0 0 -1 V -1.002 V Negative Full Scale - 1 LSB 1 REV. B -9- AD9040A U4 74AC574 2 3 4 5 6 7 AIN BNC J1 R1 51 BNC J2 R2 51 CLK U1 CLK 74HC86 1 3 +5V 2 9 10 U1 74HC86 8 -5V -5V -5V +5V +5V U1 74HC86 4 5 6 +5V GND GND U1 74HC86 12 11 13 GND GND GND -5V C1 0.1 F J7 C2 0.1 F J8 C4 0.1 F J9 -5V C14 0.1 F C15 0.1 F C16 0.1 F C17 0.1 F C13 0.1 F C5 10 F GND C3 10 F -5V +5V 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 19 18 17 16 15 14 13 12 U5 AD9721BR GND -5V D9 U3 74AC574 9 D7 8 D6 D5 D4 5 D3 GND GND GND GND GND BPREF NC D2 D1 D0 (LSB) 3 2 4 7 6 8D 7D 6D 5D 4D 3D 2D 1D 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q D8 12 D7 13 D6 14 D5 15 D4 16 D3 17 D2 18 D1 19 D0 R18 100 R17 100 R16 100 R15 100 R14 100 D5 R13 100 R12 100 D7 R11 100 D8 R10 100 R9 100 D10 (LSB) CLOCK INVERT D9 IOUT ANA RET RSET -5V GND +5V -5V GND +5V R7 2k R5 51 D6 CAMP OUT REF IN IOUT R6 51 C6 0.1 F RC OUTPUT BNC J5 D1 (MSB) D2 D3 D4 -5V GND CAMP IN REF OUT GND -5V -5V GND C21 10 F -5V -5V E1 U2 AD9040AJR AIN VREF VOUT ENC -VS -VS -VS +VS +VS +VD (MSB) D9 D8 OR 8 9 CK OE 11 1 CK OE 11 1 +5V C7 0.1 F C8 0.1 F C9 0.1 F C10 0.1 F C11 0.1 F C12 0.1 F C18 0.1 F H40DMC J3 40 39 2 CLK 38 3 4 37 D9 5 36 D8 35 6 D7 34 7 D6 33 8 D5 9 32 D4 10 31 D3 11 30 D2 29 12 13 28 27 14 15 26 25 16 24 17 23 18 D1 22 19 D0 21 20 1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H3 #4 H4 #4 H5 #4 H6 #4 H1 H2 Figure 10. PCB Schematic -10- REV. B AD9040A -73 HARMONIC DISTORTION - dBc SIGNAL-TO-NOISE RATIO - dB SIGNAL-TO-NOISE RATIO - dB 1.2 ENCODE = 40.5 MSPS -68 HARMONIC DISTORTION 66 66 DISSIPATION - Watts 1.0 60 60 -63 54 -58 SNR 48 -53 42 -48 1 2 4 6 10 20 FREQUENCY - MHz 40 60 100 0.8 54 A IN = 10.3 MHz 0.6 48 42 4 12 20 28 CLOCK RATE - MSPS 36 0.4 1 2 46 10 20 CLOCK RATE - MSPS 40 60 Figure 11. Power Dissipation vs. Clock Rate Figure 12. Harmonic Distortion and SNR vs. Analog Input Figure 13. SNR vs. Clock Rate 1024 LEAST SIGNIFICANT BITS - LSBs 1024 AD9040A DIGITAL OUTPUT CODE AD9040A DIGITAL OUTPUT CODE 896 768 640 512 384 256 128 0 0 5 10 15 20 25 30 35 40 45 50 TIME - ns 992 960 928 1.0 0.5 96 64 32 0 0 5 10 15 20 25 30 35 40 45 TIME - ns 50 0 0 10 20 30 CLOCK RATE - MSPS 40 Figure 14. Differential Nonlinearity vs. Clock Rate Figure 15. Transient Response Figure 16. Transient Response (Expanded View) 60 SIGNAL-TO-NOISE RATIO - dB 0 0 ENCODE = 32.2 MSPS 55 ENCODE = 32.2 MSPS ANALOG IN = 2.3 MHz SNR = 56.79 dB SNR (w/o har.) = 57.58 dB 2nd HARMONIC = -68.5 dB 3rd HARMONIC = 80.7 dB dBc -65 dBc ENCODE = 32.2 MSPS ANALOG IN = 10.3 MHZ SNR = 55.37 dB SNR (w/o har.) = 56.77 dB 2nd HARMONIC = -63.3 dB 3rd HARMONIC = -75.4 dB -65 50 ENCODE = 40.5 MSPS 45 AIN = 10.3 MHz 40 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C 0 8.0 FREQUENCY - MHz 16.1 0 8.0 8.0 FREQUENCY - MHz 16.1 Figure 17. SNR vs. Temperature Figure 18. Figure 19. 0 ENCODE = 40.5 MSPS f1 IN = 2.25 MHz @ -7 dBFS f2 IN = 2.35 MHz @ -7 dBFS 2f1 - f2 = -69.4 dBFS 2f2 - f1 = -69.2 dBFS dBc dBc 0 ENCODE = 40.5 MSPS ANALOG IN = 2.3 MHz SNR = 55.20 dB SNR (w/o har.) = 55.90 dB 2nd HARMONIC = -75.1 dB 3rd HARMONIC = -73.2 dB -65 0 ENCODE = 40.5 MSPS ANALOG IN = 10.3 MHz SNR = 53.38 dB SNR (w/o har.) = 54.31 dB 2nd HARMONIC = -64.7 dB 3rd HARMONIC = -73.7 dB -65 dBc 20.2 -65 0 2.5 FREQUENCY - MHz 5.0 0 10.1 FREQUENCY - MHz 0 10.1 FREQUENCY - MHz 20.2 Figure 20. Figure 21. Figure 22. REV. B -11- AD9040A OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 28-Lead Plastic DIP (N-28) 1.565 (39.70) 1.380 (35.10) 28 15 15 28-Lead SOIC Package (R-28) C1835a-0-5/99 28 0.550 (13.97) 0.530 (13.46) 1 14 PIN 1 0.250 (6.35) MAX 0.015 (0.38) MIN 0.140 (3.55) MIN 14 1 0.712 (18.08) 0.700 (17.78) PIN 1 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.625 (15.87) 0.600 (15.24) 0.070 (1.77) MAX SEATING PLANE 0.012 (0.30) 0.004 (0.10) 0.050 (1.27) BSC 0.019 (0.48) 0.014 (0.36) 0.104 (2.64) 0.093 (2.36) 0.015 (0.381) 0.008 (0.204) 0.013 (0.33) 0.009 (0.23) 0.04 (1.02) 0.024 (0.61) 0.419 (10.64) 0.393 (9.98) 0.300 (7.60) 0.292 (7.40) -12- REV. B PRINTED IN U.S.A. |
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